Conventional digital circuitry typically relies on a quartz crystal to provide a clock signal. Quartz crystals, however, are bulky and do not provide suitable options for size reductions. As digital devices continue to shrink in size, the use of quartz crystals for timing becomes an impediment to further volume reductions.
Microelectromechanical system (MEMS) resonators have been identified as a possible replacement for the quartz crystal. MEMS resonators also present their own drawbacks, including that the silicon which the resonators comprise exhibits a temperature drift caused by a temperature-dependent linear expansion coefficient. While advancements in thermal stability have been made, other issues remain. For example, the drive voltage and constant bias voltage of a MEMS resonator are defined by the geometrical layout of the resonator structure, and conventional layouts do not allow for the maximum voltage on-chip to be used as the bias voltage.
Challenges also exist in manufacturing MEMS resonators, particularly in integrating resonators as part of conventional CMOS processing. MEMS resonators often are provided as part of “system-in-package” products along with microchips and other related structures and components to which the resonators can provide a resonant frequency used in operation. Resonator structures as part of system-in-package configurations must be taken into consideration in package design and system production. For example, compatibility with CMOS (complementary metal-oxide-semiconductor) processing can be important as direct integration of resonator fabrication as part of CMOS processes can provide cost savings that make MEMS resonators more attractive.
In CMOS processing, the resonator can be encapsulated in a vacuum, with sealing or capping provided a silicon capping wafer in one embodiment, or by forming the cavity for the resonator using a sacrificial layer etch. The dimensions of the cavity and the techniques used to free the resonator within the cavity such that it can resonate are important considerations when considering compatibility with CMOS process integration. For example, if a resonator cavity is to have a clearance above the resonator structure of about 1 μm, use of conventional back-end CMOS processing techniques becomes impractical, as a wet chemical etch is often used to form the cavity but a minimum cavity height is required to prevent the resonator from adhering or bonding with the capping layer. This minimum height combined with a relatively thick ceiling (e.g., about 2-3 μm in embodiments) which seals the cavity increases the size of the resonator structure beyond what is practical and/or desired.